1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same. More specifically, the present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory) including memory cells having contact structures and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2006-317302, filed Nov. 24, 2006, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
The DRAM has memory cells, each of which may have a pair of a single transistor for selecting a memory cell and a single capacitor. In general, the transistor and the capacitor may be connected to each other through one or more contact plugs.
The capacitor may be formed in a hole such as a capacitor-hole in an insulating film such as an inter-layer insulator. The capacitor may include a bottom electrode, a capacitive insulating film, and a top electrode. The bottom electrode contacts with a capacitance contact plug. The capacitance contact plug may be positioned under the bottom electrode. The capacitance contact plug contacts with a cell contact plug. The cell contact plug may be positioned under the capacitance contact plug. The cell contact plug is connected to the transistor. In other words, the transistor is connected through the cell contact plug and the capacitance contact plug to the capacitor.
Increasing the degree of integration of the DRAM needs the shrinkage of each memory cell. The shrinkage of each memory cell needs to limit the plan-area in which the capacitor is present. The limited plan-area for the capacitor may result in reduced capacity of the capacitor. The reduction in the capacity of the capacitor may make it difficult for the conventional DRAM to ensure the normal memory operation thereof There was an issue of how to ensure the necessary capacity of the capacitor of each memory cell when each memory cell is shrunken. The limited plan-area for the capacitor needs increasing the height or vertical dimension of the capacitor in order to ensure the necessary capacity of the capacitor. The increased height or vertical dimension of the capacitor needs the increased thickness of the insulating film or inter-layer insulator having a capacitor hole of a high aspect ratio in which the capacitor is formed. Atypical example of the increased thickness of the insulating film or inter-layer insulator may be about 3000 nanometers.
The capacitor hole of the high aspect ratio may decrease in horizontally sectioned area as the depth thereof becomes deeper. In other words, the bottom of the capacitor hole is smaller in horizontally sectioned area than the top thereof The smaller sectioned area of the bottom of the capacitor hole results in a smaller contact area between the bottom electrode and the capacitor contact plug. Decreasing the contact area between the bottom electrode and the capacitor contact plug may increase contact resistance between the bottom electrode and the capacitor contact plug. Increasing the contact resistance may inhibit desired high performance of the DRAM.
The following descriptions are concerned with the issues caused by decreasing the contact area between the bottom electrode of the capacitor and the capacitor contact plug which contacts with the bottom electrode.
FIG. 5 is a fragmentary cross sectional elevation view illustrating a conventional DRAM having capacitors. Cell contact plugs 105 contact with transistors for selecting cells, wherein the transistors are not illustrated. Capacitor contact plugs 104 are formed in an inter-layer insulator 103. The capacitor contact plugs 104 contact with the cell contact plugs 105. An inter-layer insulator 102 is provided over the inter-layer insulator 103 and the capacitor contact plugs 104. An inter-layer insulator 100 is provided over the inter-layer insulator 102. Capacitor holes are formed in the stack of the inter-layer insulators 102 and 100. The capacitor holes reach the top surfaces of the capacitor contact plugs 104. Capacitors are provided in the capacitor holes. Each capacitor includes a bottom electrode 106, a capacitive insulating film 107 and a top electrode 108. The bottom electrode 106 is provided on the bottom and side walls of each capacitor hole, so that the bottom electrode contacts with the capacitor contact plug 104. The capacitive insulating film 107 is provided on the bottom electrode 106 and the top surface of the inter-layer insulator 100. The capacitive insulating film 107 is common to the capacitors. The top electrode 108 is provided on the capacitive insulating film 107 so that the top electrode 108 is separated from the bottom electrode 106 by the capacitive insulating film 107.
As shown in FIG. 5, the capacitor holes are coaxially misaligned to the capacitor contact plugs 104 even the bottom electrodes 106 contact with the capacitor contact plug 104. The coaxial misalignment of the capacitor holes to the capacitor contact plugs 104 reduces a contact area A2 between each capacitor and the corresponding capacitor contact plug 104.
FIG. 6 is a fragmentary cross sectional elevation view illustrating the capacitor holes of the conventional DRAM having capacitors. In the inter-layer insulator 100, the capacitor holes 101 are formed. The inter-layer insulator 100 may in general be made of silicon oxide. The known anisotropic etching process can be used to form capacitor holes 101 in the silicon oxide inter-layer insulator. The anisotropic etching process uses, as a main etchant, fluorine ions that are field-accelerated in high frequency plasma.
The capacitor holes 101 may in general have a center axis which is vertical to the surface of the semiconductor substrate on which the DRAM is formed. In the anisotropic etching process, fluorine ions are field-accelerated in the direction vertical to the surface of the semiconductor substrate. In some cases, field distribution in the capacitor holes 101 may vary so as to change the acceleration direction of fluorine ions. The orbit of the field-accelerated fluorine ions may have a curvature but be not straight. In this case, the capacitor holes 101 as formed may have a curvature B. The curvature B of the capacitor holes 101 may further reduce the contact area between the bottom electrode 106 and the capacitor contact plug 104 in addition to the above-described misalignment between the capacitor holes 101 and the capacitor contact plugs 104. Further reduction of the contact area may further increase the contact resistance between the capacitor and the capacitor contact plugs 104.
FIG. 7 is a fragmentary cross sectional elevation view illustrating the capacitor holes of the other conventional DRAM having capacitors. Each capacitor contact plug in the capacitor contact hole 101 has a contact pad that is wider than other portion. The contact pad is greater in horizontally sectioned area than the pother portion. The contact pad provides larger contact area A4 with the bottom electrode 106 in the capacitor hole.
The contact pad also provides larger allowance for misalignment between the capacitor hole and the capacitor contact plug under the condition for ensuring the minimum necessary contact area A4. The contact pad is suitable for increasing the density of the memory cells.
The capacitor contact plugs 101 having contact pads are made of silicon. If the bottom electrodes of the capacitors are made of a metal, a metal barrier layer needs to be interposed between the metal bottom electrode and the silicon contact pad in order to prevent reaction of silicon with the metal. Further, a silicide layer needs to be formed between the metal barrier layer and the silicon contact pad in order to reduce the contact resistance between the metal barrier layer and the silicon contact pad. The metal barrier layer may be made of titanium nitride. The silicide layer may be made of titanium silicide.
The metal barrier layer and the silicide layer may be formed as follows. Capacitor holes 101 are formed in an inter-layer insulator 100 so that parts of the top surfaces of the contact pads of the silicon capacitor contact plugs are shown through the capacitor holes 101. A chemical vapor deposition (CVD) process is carried out to supply titanium on the surfaces of the silicon contact pads, and a silicidation reaction is caused to form titanium silicide films on the surfaces of the silicon contact pads. Subsequently, metal barrier layers of titanium nitride are formed on the titanium silicide films. When the capacitor holes 101 have a high aspect ratio or a greater depth, an insufficient amount of titanium may be supplied on the surface of each silicon contact pad, thereby causing an abnormal silicidation reaction. As a result, a desired or intended silicide layer can not be formed.
FIG. 8 is a fragmentary cross sectional elevation view illustrating the capacitor holes of the other conventional DRAM having capacitors. High aspect ratio or larger depth of the capacitor holes may cause insufficient amount of titanium to be supplied on the bottoms of the capacitor holes, thereby forming undesired or unintended silicide layers of off-stoichiometric composition on the surfaces of the silicon contact pads. The silicide layers of off-stoichiometric composition may be highly resistive. Further, silicon migration can be caused, thereby forming voids on the surfaces of the silicon contact pads. Such voids may cause bad connection between the bottom electrode 106 and the silicon contact pads. The likelihood of causing these problems may depend upon the depth of the capacitor holes 101.
Japanese Unexamined Patent Application, First Publication, No. 2002-083881 discloses a conventional technique to prevent the last-mentioned problem with the off-stoichiometric composition of the silicide layers. The conventional technique is to avoid the above-described abnormal silicidation that results in off-stoichiometric composition of the silicide layers. After the capacitor contact plug is formed in a lower inter-layer insulator, a metal barrier layer including a stack of TiN/Ti layers is formed on the surface of the capacitor contact plug. Then, an upper inter-layer insulator is formed over the lower inter-layer insulator and a capacitor hole is formed in the upper inter-layer insulator, wherein the capacitor hole reaches the metal barrier layer.
The contact pad of the capacitor contact plug increases the contact area between the bottom electrode and the capacitor contact plug. When the bottom electrode is made of a metal or a metal compound, the abnormal silicidation reaction can be caused thereby making it difficult to ensure the electronic connection between the capacitor contact plug and the bottom electrode of the capacitor.
In accordance with the conventional technique disclosed in Japanese Unexamined Patent Application, First Publication, No. 2002-083881, the barrier layer covering the surface of the contact plug can prevent abnormality of silicidation reaction. This structure may, however, not prevent the other problem with misalignment between the capacitor contact plug and the capacitor hole. As described above, the misalignment decreases the contact area between the capacitor contact plug and the bottom electrode of the capacitor, thereby making it difficult to ensure the minimum necessary contact area for obtaining sufficiently reduced contact resistance between the capacitor contact plug and the bottom electrode of the capacitor.
In accordance with the conventional method of forming a capacitor having a bottom electrode of a metal or a metallic compound which is connected to a capacitor contact plug, it is not easy both to prevent the abnormality of silicidation reaction on the interface between the capacitor contact plug and the bottom electrode of the capacitor and to ensure a sufficiently large contact area between them and reduce the contact resistance between them. This results in decreasing the yield of manufacturing the semiconductor device.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved semiconductor device and/or method for forming the same. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.